The hottest solution to reduce peak EMI

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Peak EMI reduction solution

w181 series is a new device (w/02/03) launched by cypress company in 2000. This series combines the latest technology of PLL spread spectrum frequency synthesis. By frequency modulation of the output through a low-frequency carrier, Peak EMI will be greatly reduced. The application of this technology enables the system to pass the increasingly difficult EMI test without expensive shielding measures or redesign due to failure

--- in the system, EMI is weakened not only in various clock lines, but also in all signals synchronized with the clock. Moreover, the benefits of using this technology also increase with the increase of the number of addresses and data buses in the system

spread spectrum control (active at low level). Maintain this low-level signal to turn on the internal modulation waveform and enter the spread spectrum mode. There is an internal pull-down resistor at this end

--- the main features of w181 series are: the optimal weakened EMI clock signal is generated at the output end; Output frequency selection; The input of -1.25% or -3.75% can be expanded downward; Loop filter elements are integrated inside; 3.3 V or 5V working voltage according to the agreement; 8-pin SOIC or 14 pin tssop package

- this exhibition is jointly sponsored by the China Association of higher education and China National Corporation of teaching instruments and equipment --- the key technical specifications are: working voltage: vdd=3.3v 5% or vdd=5v 10%; Frequency range: 28MHz fin 75MHz; Crystal oscillator reference frequency range: 28MHz fin 40MHz; Cycle deviation: 300ps (maximum); Optional expansion ratio: -1.25% or -3.75%; Output duty cycle: 40/60% (worst case); Output rise and fall time: 5ns (maximum)

--- pin arrangement and pin function

--- w/02/03 has 8-pin SOIC package and 14 pin tssop package, and its typical application circuit block diagram and three kinds of package pin arrangement are shown in Figure 1

--- function description

--- w181 adopts frequency phase locked loop (PLL) technology to modulate the input clock. As a result, an output clock is obtained, and its frequency can slowly sweep a narrow band close to the input signal. The basic circuit structure is shown in Figure 2

--- the input reference signal is divided by Q through the frequency divider and then input into the phase discriminator. The signal from VCO is divided by P by the feedback divider and then sent to the phase detector to carry the banner of new material development. The PLL forces the frequency of the VCO output signal to change until the divided output signal and the divided reference signal match at the input of the phase detector. The output frequency is equal to the proportional multiple of p/q of the reference frequency (Note: for w181, the output frequency is equal to the input frequency). The uniqueness of spread spectrum frequency clock generation is that a modulated waveform is superimposed at the input before entering the VCO, which makes the output of the VCO slowly sweep through the preset frequency band

--- use ssftg for frequency selection

--- in the generation of spread spectrum clock, EMI attenuation depends on shaping, modulation rate and the frequency of modulation waveform. When the frequency of shaping and modulating waveform is determined by the determined frequency, the percentage of modulating not only makes the equipment have a reasonable and simple operation mode will be different. The frequency range can be set by using the frequency selection bits (FS1 and fs2). The expansion rate is also set to -1.25%. See Table 2. The high expansion rate strengthens the reduction of EMI. However, the high expansion rate may affect the performance because it exceeds the maximum rated frequency of the system or is lower than the average frequency. In view of the above reasons, the expansion rate is mostly between 0.5% and 2.5%

--- generation of spread spectrum timing signal

--- the benefits of using spread spectrum timing signal generation are shown in Figure 3. It shows the distribution of a clock harmonic EMI. Compare the EMI of a typical clock with the EMI generated by the cypress spread spectrum frequency timing signal. Please pay attention to the peak signal in the typical clock, which makes the quasi Peak EMI test of the system fade. After spectrum expansion, the peak energy will be greatly reduced (at least 8dB), because the energy is distributed through a wider bandwidth

--- modulation waveform

--- the shaping of modulation waveform with EMI weakening is very critical. The modulation scheme is used to minimize EMI, as shown in Figure 4. The modulation period is in percentage of the period length on the x-axis. The y-axis represents different frequency values and is also in percentage of the total extended frequency

--- the frequency selection table of cypress expresses the modulation percentage in two ways. The first method is to express the extended frequency band as the percentage of the average output frequency of program control, which is symmetrical about the average frequency of program control. This method is usually found in the formula fcenter Xmod% used in the frequency expansion selection table. The second method is to specify the maximum operating frequency and spread band as its percentage. The output signal sweeps from the low end of the frequency band to the maximum frequency. The expression of this method is Fmax Xmod%. No matter when this expression is used, it should be ensured that the maximum frequency will not exceed the limit. This is very important in applications where the clock drives the device at the maximum clock speed

--- Application guide

--- in order to give full play to the best performance in system application, the power decoupling scheme shown in Figure 5 should be used

--- VDO decoupling is very important to reduce phase jitter and EMI radiation. The 0.1 f decoupling capacitor should be placed as close to VDD as possible, otherwise the parasitic inductance of the wiring will eliminate its decoupling ability. The 10 f decoupling capacitor in Figure 5 should be tantalum capacitor

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